library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;

entity tb_processor is
end tb_processor;

architecture structure of tb_processor is
	component processor
		port (
        clock : in std_ulogic;
        reset : in std_ulogic;
        d_busout : out std_logic_vector(31 downto 0);
        d_busin : in std_logic_vector(31 downto 0);
        a_bus : out std_logic_vector(31 downto 0);
        write : out std_ulogic;
        read : out std_ulogic;
        ready : in std_ulogic
        );
	end component;
	
	component memory
        generic (width: integer := 32; tpd: time := 1 ns);
		port (
        d_bus_out: out std_logic_vector(width-1 downto 0);
        d_bus_in : in  std_logic_vector(width-1 downto 0);
        a_bus    : in  std_logic_vector(width-1 downto 0);
        read     : in  std_ulogic;
        write    : in  std_ulogic;
        ready    : out std_ulogic
        );
	end component;
	
    signal write, read_s, ready : std_ulogic;
    signal d_bus_to_mem, d_bus_to_proc, a_bus : std_logic_vector(31 downto 0);
    signal clock : std_ulogic := '0';
	signal reset : std_ulogic := '1';
    
begin
	duv: processor
		port map (clock=>clock, reset=>reset, d_busout=>d_bus_to_mem, d_busin=>d_bus_to_proc,
                a_bus=>a_bus, write=>write, read=>read_s, ready=>ready);
        
	tvc: memory
		port map (d_bus_out=>d_bus_to_proc, d_bus_in=>d_bus_to_mem,
                a_bus=>a_bus, read=>read_s, write=>write, ready=>ready);
    
    clock <= not clock after 10 ns;
	reset <= '1', '0' after 40 ns;
end structure;

